1. Field of the Invention
The present invention relates to the field of electronic circuits. More specifically, embodiments of the present invention relate to adders, and in particular, adders included in a pipelined processor.
2. Description of the Related Art
Users of data processing systems continue to demand greater performance for handling increasingly complex and difficult tasks. Greater performance from the processors that operate such systems may be obtained through faster clock speeds, so that individual instructions are processed more quickly. However, relatively greater performance gains have been achieved through performing multiple operations in parallel with one another.
One manner of parallelization is known as “pipelining”, where instructions are fed into a pipeline for an execution unit in a processor that performs different operations necessary to process the instructions in parallel. For example, to process a typical instruction, a pipeline may include separate stages for fetching the instruction from memory, executing the instruction, and writing the results of the instruction back into memory. Thus, for a sequence of instructions fed in sequence into the pipeline, as the results of the first instruction are being written back into memory by the third stage of the pipeline, a next instruction is being executed by the second stage, and still a next instruction is being fetched by the first stage. While each individual instruction may take several clock cycles to be processed, since other instructions are also being processed at the same time, the overall throughput of the processor is much greater. With respect to pipelining, the term “stage” generally refers to the combinational logic between registers or latches.
Pipelining is the placing of logic between various types of memories. Memories include registers, latches, and Random Access Memory (RAM). A register is a type of word-based memory that stores a set of bits, and generally, all the bits are written in parallel on the edge of a clock or similar event in time. A latch is a type of word-based memory that stores a set of bits, and generally, the bits are stored while an enable signal is active, thereby allowing input changes to propagate to outputs while the enable signal is active. A latch is sometimes called a “half-register”. Putting logic between half-registers has the advantage of partial cycle stealing from a prior stage, and can reduce the cycle time of a pipelined circuit. Random Access Memory (RAM) is an array-based memory that stores a plurality of words, each word being a set of bits. RAMs can have a plurality of access ports, thereby allowing multiple reads and/or writes from/to the RAM. Fast RAM, generally with multiple access ports, is sometimes called a register file.
Individual arithmetic operations, such as addition and multiplication, can also be pipelined. For example, a multiplier can be designed with four stages, and take four clock cycles to compute a result corresponding to a particular input, but accept new inputs each clock cycle. Pipelining can be applied to memories as well. For example, a memory could have the following stages: address decode; memory array access; and data output. A pipelined circuit can be composed of many stages, and include a plurality of memory, arithmetic, and logic circuits.
Greater parallelization can also be performed by attempting to execute multiple instructions in parallel using multiple pipelined execution units in a processor. Processors that include multiple execution units are often referred to as “superscalar” processors, and such processors include scheduling circuitry that attempts to efficiently dispatch instructions to different execution units so that as many instructions are processed at the same time as possible. Relatively complex decision-making circuitry is often required, however, because oftentimes one instruction cannot be processed until after another instruction is completed. For example, if a first instruction loads a register with a value from memory, and a second instruction adds a fixed number to the contents of the register, the second instruction typically cannot be executed until execution of the first instruction is complete.
The use of relatively complex scheduling circuitry can occupy a significant amount of circuitry on an integrated circuit device, and can slow the overall execution speed of a processor. For these reasons, significant development work has been devoted to Very Long Instruction Word (VLIW) processors, where the decision as to which instructions can be executed in parallel is made when a program is created, rather than during execution. A VLIW processor typically includes multiple pipelined execution units, and each VLIW instruction includes multiple primitive instructions known as parcels that are known to be executable at the same time as one another. Each primitive instruction in a VLIW may therefore be directly dispatched to one of the execution units without the extra overhead associated with scheduling. VLIW processors rely on sophisticated computer programs known as compilers to generate suitable VLIW instructions for a computer program written by a computer user. VLIW processors are typically less complex and more efficient than superscalar processors given the elimination of the overhead associated with scheduling the execution of instructions.
It is common practice for pipelined logic to be synchronously clocked. That is, a single timebase clocks the entire circuit. Alternatively, various portions of the pipelined logic can be clocked with different timebases (i.e., different frequencies), and these different timebases are usually (although not necessarily) rational number multiples of each other, thereby allowing them to be derived from a single frequency source. In the case of asynchronous circuits, there can be multiple timebases that are asynchronous to one another. It is also possible for registers to be clocked by detecting when the computation of input data is complete (i.e., self-timed circuits), resulting in fully asynchronous behavior.
One design consideration in pipelined circuits is the critical path. The critical path is the path through a circuit that takes the longest time to propagate from input to output. The critical path determines the smallest allowable clock period where, the smaller the clock period, the higher the performance. Accordingly, the performance is inversely related to the clock period. In pipelined circuits, this critical path is measured from register-to-register, latch-to-latch (or between any two of the various types of memory circuits), or input-to-output. In general terms, the critical path can be described as a number of gate delays. That is, the critical path is the maximum number of gates that input signals propagate through within a circuit. Hence, the fewer gate delays in the critical path of a circuit, the higher the circuit's performance.
One possible critical path in pipelined logic is through an adder. A typical adder performs both addition and subtraction. Generally, the critical path through an adder is primarily due to an arithmetic carry through all the bits. An arithmetic carry is the “carry out” from a bit position into the next most significant bit. For example, in an 8-bit adder, adding the bit patterns ‘01111111’ and ‘01111111’ causes arithmetic carries to propagate through all the bit positions. A simple type of adder allows carry values to ripple from the least significant bit to the most significant bit, but this is slow due to a long critical path. More sophisticated adders use a carry-look-ahead circuit to generate carry values. But, even for carry-look-ahead circuits, wider (i.e., more bit position) adders have a longer critical path.
Recently, microprocessor architectures have been extended from 32-bit architectures to 64-bit architectures. This change increases the width of the adders, increasing the critical path delay through the adder (e.g., by increasing the number of bits for the carry-look-ahead logic) and reducing performance. In a 64-bit processor, the critical path in the 64-bit adders could be the limiting factor in the processor's performance. Hence, it is desirable to reduce the critical path though 64-bit adders.
Typically, adders are implemented with static logic gates, and the currently popular technology is CMOS. Static gates are logic gates whose output is driven to either a “1” or “0” logic state, and do not utilize dynamic circuit properties, such as charge being stored on a non-driven node. Temporarily assuming logic gates all have about the same propagation delay, then the number of layers of logic determine the performance of the adder, and this is the maximum number of gate delays from input to output. In general, circuit designers strive to reduce the number of layers of logic in the stage of a pipelined circuit.
Another choice for the implementation of adders makes use of domino logic. Domino logic is a circuit design technique that makes use of dynamic circuits, and has the advantage of low propagation delay (i.e., they are fast circuits) and smaller area (due to fewer transistors). In domino logic, nodes are precharged during a portion of a clock cycle and conditionally discharged during another portion of the clock cycle, where the discharging phase performs the logic function. Hence, in a series of these gates, a set of nodes are all precharged, and the discharging of nodes can flow through the series of gates, analogous to a series of falling dominos. In order to provide more complicated logic functions, a large number of discharging transistors can be used in a mixture of parallel and series connections, hereinafter called a domino tree. The output from a domino tree is often buffered by an inverter, thereby isolating the dynamic node from the load. A domino tree with an output buffer constitutes one level of logic in a circuit (i.e., one gate delay).
A variation of domino logic, called complex domino logic, includes domino trees whose output is fed into static logic gates, rather than an inverter. This provides a more complex logic function because the output of multiple domino trees (i.e., the dynamic nodes) can be input to another gate. A set of domino trees with a static gate constitutes one level of logic in a circuit (i.e., one gate delay).
A variation of complex domino logic includes domino trees with both precharged high and precharged low states. For example, a first set of domino trees could be precharged high (i.e., a logic “1” state), and the outputs from this first set are input to a second set of domino trees that are precharged low (i.e., to a logic “0” state). Continuing this example, a third set of domino trees, precharged high, receive input from the output of the second set. This can be extended to any number of sets of domino trees. In this variation, an output buffer is generally not used, and therefore, two domino trees (one precharged high and one precharged low) constitute one level of logic (i.e., one gate delay).
Prior art adders use several levels of logic, or tree levels. The more levels of logic (either static or dynamic), the longer the critical path and the lower the performance. Therefore, these prior art adders are not as fast as they would be with fewer levels of logic. There are no known 64-bit adders with only three gate delays in their critical path.
Therefore, there is a need for a faster adder with fewer levels of logic.